#ifndef __MACH_LA_LS2P500_H
#define __MACH_LA_LS2P500_H

#include <asm/loongarch.h>

/* CHIP CONFIG regs */
#define LS_GENERAL_CFG0				PHYS_TO_UNCACHED(0x14000100)
#define LS_GENERAL_CFG1				PHYS_TO_UNCACHED(0x14000104)
#define LS_GENERAL_CFG2				PHYS_TO_UNCACHED(0x14000108)
#define LS_GENERAL_CFG3				PHYS_TO_UNCACHED(0x1400010c)
#define LS_GENERAL_CFG4				PHYS_TO_UNCACHED(0x14000110)
#define LS_GENERAL_CFG5				PHYS_TO_UNCACHED(0x14000114)
#define LS_SAMPLE_CFG0				PHYS_TO_UNCACHED(0x14000120)
#define LS_CHIP_HPT_LO				PHYS_TO_UNCACHED(0x14000130)
#define LS_CHIP_HPT_HI				PHYS_TO_UNCACHED(0x14000134)

#define LS_SYS_PLL_L				PHYS_TO_UNCACHED(0x15103000)
#define LS_SYS_PLL_H				PHYS_TO_UNCACHED(0x15103004)
#define LS_DDR_PLL_L				PHYS_TO_UNCACHED(0x15103008)
#define LS_DDR_PLL_H				PHYS_TO_UNCACHED(0x1510300c)
#define LS_VID_PLL_L				PHYS_TO_UNCACHED(0x15103010)
#define LS_VID_PLL_H				PHYS_TO_UNCACHED(0x15103014)

#define LS_FREQ_SCALE0				PHYS_TO_UNCACHED(0x15103020)
#define LS_FREQ_SCALE1				PHYS_TO_UNCACHED(0x15103024)
#define LS_FREQ_SCALE2				PHYS_TO_UNCACHED(0x15103028)
#define LS_CLK_ENABLE				PHYS_TO_UNCACHED(0x1510302c)

#define SYS_L1DIV_OUT_SHIFT		24
#define SYS_L1DIV_LOOPC_SHIFT		16
#define SYS_L1DIV_REF_SHIFT		8
#define SYS_L1DIV_OUT_WIDTH		6
#define SYS_L1DIV_LOOPC_WIDTH		8
#define SYS_L1DIV_REF_WIDTH		6
#define SYS_L1DIV_OUT_MARK		0x3f
#define SYS_L1DIV_LOOPC_MARK		0xff
#define SYS_L1DIV_REF_MARK		0x3f

#define SYS_L2DIV_OUT_SOC_SHIFT		8
#define SYS_L2DIV_OUT_LA132_SHIFT	0
#define SYS_L2DIV_OUT_SOC_WIDTH		6
#define SYS_L2DIV_OUT_LA132_WIDTH	6
#define SYS_L2DIV_OUT_SOC_MARK		0x3f
#define SYS_L2DIV_OUT_LA132_MARK	0x3f

#define DDR_L1DIV_OUT_SHIFT		24
#define DDR_L1DIV_LOOPC_SHIFT		16
#define DDR_L1DIV_REF_SHIFT		8
#define DDR_L1DIV_OUT_WIDTH		6
#define DDR_L1DIV_LOOPC_WIDTH		8
#define DDR_L1DIV_REF_WIDTH		6
#define DDR_L1DIV_OUT_MARK		0x3f
#define DDR_L1DIV_LOOPC_MARK		0xff
#define DDR_L1DIV_REF_MARK		0x3f

#define DDR_L2DIV_OUT_IMG_SHIFT		8
#define DDR_L2DIV_OUT_NET_SHIFT		0
#define DDR_L2DIV_OUT_IMG_WIDTH		6
#define DDR_L2DIV_OUT_NET_WIDTH		6
#define DDR_L2DIV_OUT_IMG_MARK		0x3f
#define DDR_L2DIV_OUT_NET_MARK		0x3f

#define VID_L1DIV_OUT_SHIFT		24
#define VID_L1DIV_LOOPC_SHIFT		16
#define VID_L1DIV_REF_SHIFT		8
#define VID_L1DIV_OUT_WIDTH		6
#define VID_L1DIV_LOOPC_WIDTH		8
#define VID_L1DIV_REF_WIDTH		6
#define VID_L1DIV_OUT_MARK		0x3f
#define VID_L1DIV_LOOPC_MARK		0xff
#define VID_L1DIV_REF_MARK	        0x3f

#define VID_L2DIV_OUT_GMACBP_SHIFT	8
#define VID_L2DIV_OUT_SCVID_SHIFT	0
#define VID_L2DIV_OUT_GMACBP_WIDTH	6
#define VID_L2DIV_OUT_SCVID_WIDTH	6
#define VID_L2DIV_OUT_GMACBP_MARK	0x3f
#define VID_L2DIV_OUT_SCVID_MARK	0x3f

#define FREQSCALE0_JPEG_SHIFT		28
#define FREQSCALE0_JBIG_SHIFT           24
#define FREQSCALE0_SDIO_SHIFT		20
#define FREQSCALE0_APB_SHIFT		16
#define FREQSCALE0_BOOT_SHIFT           12
#define FREQSCALE0_GMAC_SHIFT		8
#define FREQSCALE0_USB_SHIFT		4
#define FREQSCALE0_NODE_SHIFT           0
#define FREQSCALE0_JPEG_MARK		0x7
#define FREQSCALE0_JBIG_MARK            0x7
#define FREQSCALE0_SDIO_MARK		0x7
#define FREQSCALE0_APB_MARK		0x7
#define FREQSCALE0_BOOT_MARK		0x7
#define FREQSCALE0_GMAC_MARK		0x7
#define FREQSCALE0_USB_MARK		0x7
#define FREQSCALE0_NODE_MARK		0x7

#define FREQSCALE1_AES_SHIFT		28
#define FREQSCALE1_RSMXBAR_SHIFT        24
#define FREQSCALE1_LSCVID_SHIFT		20
#define FREQSCALE1_PRVID_SHIFT		16
#define FREQSCALE1_PRIFC_SHIFT          12
#define FREQSCALE1_PRDEV_SHIFT		8
#define FREQSCALE1_PRXBAR_SHIFT		4
#define FREQSCALE1_PR132_SHIFT          0
#define FREQSCALE1_AES_MARK		0x7
#define FREQSCALE1_RSMXBAR_MARK         0x7
#define FREQSCALE1_LSCVID_MARK		0x7
#define FREQSCALE1_PRVID_MARK		0x7
#define FREQSCALE1_PRIFC_MARK		0x7
#define FREQSCALE1_PRDEV_MARK		0x7
#define FREQSCALE1_PRXBAR_MARK		0x7
#define FREQSCALE1_PR132_MARK		0x7


#define FREQSCALE2_SCIFC_SHIFT          12
#define FREQSCALE2_SCDEV_SHIFT		8
#define FREQSCALE2_SCXBAR_SHIFT		4
#define FREQSCALE2_SC132_SHIFT          0

#define FREQSCALE2_SCIFC_MARK		0x7
#define FREQSCALE2_SCDEV_MARK		0x7
#define FREQSCALE2_SCXBAR_MARK		0x7
#define FREQSCALE2_SC132_MARK		0x7


#define LS_GPIO_O_OFFSET                        0x10
#define LS_GPIO_I_OFFSET                        0x20
#define LS_GPIO_INT_EN_OFFSET                   0x30
#define LS_GPIO_INT_POL_OFFSET                  0x40
#define LS_GPIO_INT_EDGE_OFFSET                 0x50
#define LS_GPIO_INT_CLR_OFFSET                  0x60
#define LS_GPIO_INT_STS_OFFSET                  0x70
#define LS_GPIO_INT_DUAL_OFFSET                 0x80

#define LS_GPIO_SKIP_64_OFFSET			(0x20)

#define LS_MAIN_GPIO_BASE               PHYS_TO_UNCACHED(0x14202000)
#define LS_GPIO_00_31_DIR			    PHYS_TO_UNCACHED(LS_MAIN_GPIO_BASE)
#define LS_GPIO_32_63_DIR			    PHYS_TO_UNCACHED(LS_MAIN_GPIO_BASE+4)
#define LS_GPIO_00_31_IN			    PHYS_TO_UNCACHED(LS_MAIN_GPIO_BASE + LS_GPIO_I_OFFSET)
#define LS_GPIO_32_63_IN			    PHYS_TO_UNCACHED(LS_MAIN_GPIO_BASE + LS_GPIO_I_OFFSET +4)
#define LS_GPIO_00_31_OUT			    PHYS_TO_UNCACHED(LS_MAIN_GPIO_BASE + LS_GPIO_O_OFFSET)
#define LS_GPIO_32_63_OUT			    PHYS_TO_UNCACHED(LS_MAIN_GPIO_BASE + LS_GPIO_O_OFFSET +4)

#define LS_PRT_GPIO_BASE                PHYS_TO_UNCACHED(0x15102000)
#define LS_PRT_GPIO_00_31_DIR			PHYS_TO_UNCACHED(LS_PRT_GPIO_BASE)
#define LS_PRT_GPIO_32_63_DIR			PHYS_TO_UNCACHED(LS_PRT_GPIO_BASE+4)
#define LS_PRT_GPIO_00_31_IN			PHYS_TO_UNCACHED(LS_PRT_GPIO_BASE + LS_GPIO_I_OFFSET)
#define LS_PRT_GPIO_32_63_IN			PHYS_TO_UNCACHED(LS_PRT_GPIO_BASE + LS_GPIO_I_OFFSET +4)
#define LS_PRT_GPIO_00_31_OUT			PHYS_TO_UNCACHED(LS_PRT_GPIO_BASE + LS_GPIO_O_OFFSET)
#define LS_PRT_GPIO_32_63_OUT			PHYS_TO_UNCACHED(LS_PRT_GPIO_BASE + LS_GPIO_O_OFFSET +4)

#define LS_SCA_GPIO_BASE                PHYS_TO_UNCACHED(0x15201000)
#define LS_SCA_GPIO_00_31_DIR			PHYS_TO_UNCACHED(LS_SCA_GPIO_BASE)
#define LS_SCA_GPIO_32_63_DIR			PHYS_TO_UNCACHED(LS_SCA_GPIO_BASE+4)
#define LS_SCA_GPIO_00_31_IN			PHYS_TO_UNCACHED(LS_SCA_GPIO_BASE + LS_GPIO_I_OFFSET)
#define LS_SCA_GPIO_32_63_IN			PHYS_TO_UNCACHED(LS_SCA_GPIO_BASE + LS_GPIO_I_OFFSET +4)
#define LS_SCA_GPIO_00_31_OUT			PHYS_TO_UNCACHED(LS_SCA_GPIO_BASE + LS_GPIO_O_OFFSET)
#define LS_SCA_GPIO_32_63_OUT			PHYS_TO_UNCACHED(LS_SCA_GPIO_BASE + LS_GPIO_O_OFFSET +4)

#define LS_GPIO_0_15_MULTI_CFG			PHYS_TO_UNCACHED(0x14000490)
#define LS_GPIO_16_31_MULTI_CFG			PHYS_TO_UNCACHED(0x14000494)
#define LS_GPIO_32_43_MULTI_CFG			PHYS_TO_UNCACHED(0x14000498)

#define LS_PRT_GPIO_0_15_MULTI_CFG		PHYS_TO_UNCACHED(0x15103040)
#define LS_PRT_GPIO_16_31_MULTI_CFG		PHYS_TO_UNCACHED(0x15103044)
#define LS_PRT_GPIO_32_47_MULTI_CFG		PHYS_TO_UNCACHED(0x15103048)
#define LS_PRT_GPIO_48_57_MULTI_CFG		PHYS_TO_UNCACHED(0x1510304c)

#define LS_GPIO_IRQ_EN_CFG			    PHYS_TO_UNCACHED(0x140004e0)
#define LS_USB_PHY_CFG0				    PHYS_TO_UNCACHED(0x14000500)
#define LS_USB_PHY_CFG1				    PHYS_TO_UNCACHED(0x14000504)


#define writel_reg_bit(addr, clear_bit, bit_val)	(*(volatile unsigned int*)(addr)) = (*(volatile unsigned int*)(addr)) & (~clear_bit) | bit_val

/* OTG regs */

/* USB regs */
#define LS_EHCI_BASE				PHYS_TO_UNCACHED(0x14030000)
#define LS_OHCI_BASE				PHYS_TO_UNCACHED(0x14038000)

/* GMAC regs */
#define LS_GMAC0_BASE               PHYS_TO_UNCACHED(0x14140000)
#define LS_GMAC1_BASE               PHYS_TO_UNCACHED(0x14020000)

/* DC regs */


/* SPI regs */
#define LS_SPI0_BASE				PHYS_TO_UNCACHED(0x14010000)
#define LS_SPI1_BASE				PHYS_TO_UNCACHED(0x14203000)
#define LS_SPI2_BASE				PHYS_TO_UNCACHED(0x15109000)
#define LS_SPI3_BASE				PHYS_TO_UNCACHED(0x15203000)

/* UART regs */
#define LS_UART0_REG_BASE			PHYS_TO_UNCACHED(0x14200000)
#define LS_UART1_REG_BASE			PHYS_TO_UNCACHED(0x14200400)
#define LS_UART2_REG_BASE			PHYS_TO_UNCACHED(0x14200800)
#define LS_UART3_REG_BASE			PHYS_TO_UNCACHED(0x14200c00)
#define LS_UART4_REG_BASE			PHYS_TO_UNCACHED(0x15100000)
#define LS_UART5_REG_BASE			PHYS_TO_UNCACHED(0x15100800)
#define LS_UART6_REG_BASE			PHYS_TO_UNCACHED(0x15200000)
#define LS_UART7_REG_BASE			PHYS_TO_UNCACHED(0x15200800)


/* I2C regs */
#define LS_I2C0_REG_BASE			PHYS_TO_UNCACHED(0x14201000)
#define LS_I2C0_PRER_LO_REG			(LS_I2C0_REG_BASE + 0x0)
#define LS_I2C0_PRER_HI_REG			(LS_I2C0_REG_BASE + 0x1)
#define LS_I2C0_CTR_REG				(LS_I2C0_REG_BASE + 0x2)
#define LS_I2C0_TXR_REG				(LS_I2C0_REG_BASE + 0x3)
#define LS_I2C0_RXR_REG				(LS_I2C0_REG_BASE + 0x3)
#define LS_I2C0_CR_REG				(LS_I2C0_REG_BASE + 0x4)
#define LS_I2C0_SR_REG				(LS_I2C0_REG_BASE + 0x4)

#define LS_I2C1_REG_BASE			PHYS_TO_UNCACHED(0x14201800)
#define LS_I2C1_PRER_LO_REG			(LS_I2C1_REG_BASE + 0x0)
#define LS_I2C1_PRER_HI_REG			(LS_I2C1_REG_BASE + 0x1)
#define LS_I2C1_CTR_REG				(LS_I2C1_REG_BASE + 0x2)
#define LS_I2C1_TXR_REG				(LS_I2C1_REG_BASE + 0x3)
#define LS_I2C1_RXR_REG				(LS_I2C1_REG_BASE + 0x3)
#define LS_I2C1_CR_REG				(LS_I2C1_REG_BASE + 0x4)
#define LS_I2C1_SR_REG				(LS_I2C1_REG_BASE + 0x4)

#define LS_I2C2_REG_BASE			PHYS_TO_UNCACHED(0x15101000)
#define LS_I2C2_PRER_LO_REG			(LS_I2C2_REG_BASE + 0x0)
#define LS_I2C2_PRER_HI_REG			(LS_I2C2_REG_BASE + 0x1)
#define LS_I2C2_CTR_REG				(LS_I2C2_REG_BASE + 0x2)
#define LS_I2C2_TXR_REG				(LS_I2C2_REG_BASE + 0x3)
#define LS_I2C2_RXR_REG				(LS_I2C2_REG_BASE + 0x3)
#define LS_I2C2_CR_REG				(LS_I2C2_REG_BASE + 0x4)
#define LS_I2C2_SR_REG				(LS_I2C2_REG_BASE + 0x4)

#define LS_I2C3_REG_BASE			PHYS_TO_UNCACHED(0x15101800)
#define LS_I2C3_PRER_LO_REG			(LS_I2C3_REG_BASE + 0x0)
#define LS_I2C3_PRER_HI_REG			(LS_I2C3_REG_BASE + 0x1)
#define LS_I2C3_CTR_REG				(LS_I2C3_REG_BASE + 0x2)
#define LS_I2C3_TXR_REG				(LS_I2C3_REG_BASE + 0x3)
#define LS_I2C3_RXR_REG				(LS_I2C3_REG_BASE + 0x3)
#define LS_I2C3_CR_REG				(LS_I2C3_REG_BASE + 0x4)
#define LS_I2C3_SR_REG				(LS_I2C3_REG_BASE + 0x4)

#define CR_START				0x80
#define CR_STOP					0x40
#define CR_READ					0x20
#define CR_WRITE				0x10
#define CR_ACK					0x8
#define CR_IACK					0x1

#define SR_NOACK				0x80
#define SR_BUSY					0x40
#define SR_AL					0x20
#define SR_TIP					0x2
#define	SR_IF					0x1

/* PWM regs */
#define LS_MAIN_PWM0_REG_BASE			PHYS_TO_UNCACHED(0x14207000)
#define LS_PRT_PWM0_REG_BASE			PHYS_TO_UNCACHED(0x15107000)

/* SDIO regs */
#define LS_SDIO0_BASE 				PHYS_TO_UNCACHED(0x14210000)
#define LS_SDIO1_BASE 				PHYS_TO_UNCACHED(0x14218000)

/* HPET regs */
#define LS_HPET0_BASE 				PHYS_TO_UNCACHED(0x14204000)
#define LS_HPET0_PERIOD				(LS_HPET0_BASE + 0x4)
#define LS_HPET0_CONF				(LS_HPET0_BASE + 0x10)
#define LS_HPET0_MAIN				(LS_HPET0_BASE + 0xF0)

#define LS_HPET1_BASE 				PHYS_TO_UNCACHED(0x14208000)
#define LS_HPET2_BASE 				PHYS_TO_UNCACHED(0x1510b000)
#define LS_HPET3_BASE 				PHYS_TO_UNCACHED(0x15205000)

/* DMA regs */
/*gmac0 dma*/
#define LS_DMA_ORDER0				PHYS_TO_UNCACHED(0x14141000)
/*gmac1 dma*/
#define LS_DMA_ORDER1				PHYS_TO_UNCACHED(0x14020000)


/* RTC regs */
#define LS_RTC_REG_BASE				PHYS_TO_UNCACHED(0x1510a00)
#define	LS_TOY_TRIM_REG				(LS_RTC_REG_BASE + 0x0020)
#define	LS_TOY_WRITE0_REG			(LS_RTC_REG_BASE + 0x0024)
#define	LS_TOY_WRITE1_REG			(LS_RTC_REG_BASE + 0x0028)
#define	LS_TOY_READ0_REG			(LS_RTC_REG_BASE + 0x002c)
#define	LS_TOY_READ1_REG			(LS_RTC_REG_BASE + 0x0030)
#define	LS_TOY_MATCH0_REG			(LS_RTC_REG_BASE + 0x0034)
#define	LS_TOY_MATCH1_REG			(LS_RTC_REG_BASE + 0x0038)
#define	LS_TOY_MATCH2_REG			(LS_RTC_REG_BASE + 0x003c)
#define	LS_RTC_CTRL_REG				(LS_RTC_REG_BASE + 0x0040)
#define	LS_RTC_TRIM_REG				(LS_RTC_REG_BASE + 0x0060)
#define	LS_RTC_WRITE0_REG			(LS_RTC_REG_BASE + 0x0064)
#define	LS_RTC_READ0_REG			(LS_RTC_REG_BASE + 0x0068)
#define	LS_RTC_MATCH0_REG			(LS_RTC_REG_BASE + 0x006c)
#define	LS_RTC_MATCH1_REG			(LS_RTC_REG_BASE + 0x0070)
#define	LS_RTC_MATCH2_REG			(LS_RTC_REG_BASE + 0x0074)

#define LS_SCACHE_LOCK_WIN0_BASE                PHYS_TO_UNCACHED(0x14000200)
#define LS_SCACHE_LOCK_WIN1_BASE                PHYS_TO_UNCACHED(0x14000208)
#define LS_SCACHE_LOCK_WIN2_BASE                PHYS_TO_UNCACHED(0x14000210)
#define LS_SCACHE_LOCK_WIN3_BASE                PHYS_TO_UNCACHED(0x14000218)
#define LS_SCACHE_LOCK_WIN0_MASK                PHYS_TO_UNCACHED(0x14000240)
#define LS_SCACHE_LOCK_WIN1_MASK                PHYS_TO_UNCACHED(0x14000248)
#define LS_SCACHE_LOCK_WIN2_MASK                PHYS_TO_UNCACHED(0x14000250)
#define LS_SCACHE_LOCK_WIN3_MASK                PHYS_TO_UNCACHED(0x14000258)


#define LS_MAIN_WDT                             PHYS_TO_UNCACHED(0x14205000)
#define LS_PRT_WDT                              PHYS_TO_UNCACHED(0x15103900)
#define LS_SCA_WDT                              PHYS_TO_UNCACHED(0x15202900)

#define LS_RST_CNT_REG	                        (LS_MAIN_WDT)
#define LS_WD_TIMER_REG                         (LS_MAIN_WDT + 0x4)
#define LS_WD_SET_REG	                        (LS_MAIN_WDT + 0x8)
#define LS_PLTRST_SET_REG	                    (LS_MAIN_WDT + 0xc)

#define LS_MAIN_GPIO_PINMUX_CFG                 PHYS_TO_UNCACHED(0x14000490)

/*not use acpi */
#define NOT_USE_ACPI

#endif /* __MACH_LA_LS2P500_H */
